Organizing, Analyzing & Verification tools for HDL designs, FPGAs, Board schematic, PCB layout and Systems designers

For more information:

Ohad Beit-On

ohad@sightsys.co.il

054-2584032

 

HDL Works offers high-performance, intuitive SW tools for complex HDL design and FPGA / PCB verification

 

 

 

ConnTrace – Viewing connections between large components on one or multiple PCBs and FPGAs

 

IO Checker FPGA versus PCB pin assignment verification

 

HDL Companion – The SWISS Army knife for every HDL Design Engineer

 

EASE – Graphical HDL Entry

 

 

 

 

 

 

 

 

 

 

 

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ConnTRACE – Viewing connections between large components
on one or multiple PCBs and FPGAs

Complex electronic systems consist of one or more PCBs. They can be connected using a backplane, daughter boards and/or cables. Each schematic has to be manually checked for the correct signal names. Verifying interconnect between components on different boards is even more tedious. ConnTrace offers an easy and smart way to organize and view the schematic data.
Instead of comparing two lists with hundreds of pins for each connector manually, or browsing through a netlist file, you can load all the PCB netlist files in ConnTrace and define how boards are connected.

Netlist view

ConnTrace has an unique tabular netlist view which shows the netlist and selected (large) components (over multiple boards). The view (with the various sorting and filter options) makes it easy to see how components are connected.

Intelligent Verification

Quite often the signal names are different on the connected boards, but are correctly connected. ConnTrace uses rules (based on regular expressions) to match the signal names between PCBs. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all connector pins.

The flexibility of ConnTrace allows it to be used in any design flow and does not require any design methodology. The rule generator in combination with the sorted problem view allows engineers to validate large systems in a few hours.

Once the project and the connections between boards are defined it is a simple task to re-verify the connectivity when changes were made to the PCBs or FPGAs. All out-of-date files can be processed in one action.

 

FPGAs

Any FPGA present on a board can be visualized as (virtual) board based on information extracted from the pin report file (generated by your FPGA development tool) or an constraint file. This allows you to easily see how the FPGA IO signals connect to the other boards and FPGAs in your system.

Features & Benefits

  • View connectivity between large components
  • Compare PCB signal/pin names using regular expressions
  • Automatic rule generation
  • User directed acceptance of verified differences
  • Allows different boards formats in one project
  • Connector pin mapping for OPENVPX
  • Concentrate on a dozen differences instead of a thousand lines
  • Fits in any design flow
  • HTML report
ConnTrace Main Window
ConnTrace application

Explore ConnTrace features:

Latest release

More information

Data SheetData Sheet (PDF)

 

 

 

 

 

 

 

 

 

 

 

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IO Checker – Verifying a 1000+ FPGA IO pins between PCB and FPGA in 30 minutes

When using placing a large FPGA on a PCB making sure that the FPGA pins are connected to the right signals on the PCB is a cumbersome task. On the FPGA side the pins are assigned to the HDL signals that form the top level of the logic implemented on the FPGA. On the PCB side the pins have to be connected to the proper net that will connect it to other components on the PCB. Because implementation of FPGA and PCB is often done in parallel and by different engineers, the signal names used are not always identical. To make things even worse, it is often necessary to perform pin swaps to prevent PCB routing problems. These pin swaps have to be made both on the FPGA and the PCB. As this is almost always manual work, and current devices have over 1500 pins, a mistake is easily made.
IO Checker Main Window
IO Checker main window

Intelligent Verification

IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.

The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour.

Once the project and its rules are defined it is a simple task to keep the FPGA and PCB data consistent. All out-of-date files are processed in one action and all changes are reported.


Verifying an FPGA
in 6 Minutes


Creating constraints
in 8 minutes

IO Checker overview

Features & Benefits

  • Compare FPGA and PCB pin names using regular expressions
  • Create & update FPGA constraint file
  • Automatic rule generation
  • Voltage checks for power pins
  • User directed acceptance of verified differences
  • One click verification and consistency
  • Reports incremental changes in pin- and net list
  • Concentrate on a dozen differences instead of a thousand lines
  • Fits in any design flow
  • HTML report

Explore IO Checker features

Other IO Checker details

Altium Designer schematic wired by IO Checker.
Altium Designer schematic wired by IO Checker

 

 

 

 

 

 

 

 

 

 

 

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HDL Companion – is the HDL designer’s Swiss army knife

It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources. Complete design directories and design files are dragged into HDL Companion and a complete design overview is created in seconds, uncovering information regarding numerous aspects of the design. The GUI offers many ways to navigate through the design and explore the details you’re looking for.
The embedded fuzzy parsers accept any SystemVerilog, VHDL or mixed HDL design code; even if the code is incomplete or contains errors. Syntactically correct HDL can also be linted to find problems not reported by the compilers.

HDL Companion HDL Companion has a unique setup of three main windows and a console window, which together offer a complete overview of your design, from high level structure to the details in the source code. The excellent navigation capabilities, including signal tracing, offer you an easy way to find an object and show its details.
The Console Window shows all syntax errors and warnings, which can easily be located in the HDL source using hot links from the Console Window to the Scriptum Window. The Console Window also functions as a Tcl interpreter, where any Tcl script or shell command can be executed.

Other features include a language sensitive text editor, revision control and interfaces to all major simulation and synthesis tools.

 

Explore HDL Companion Features

Supported Platforms and Licensing

What is new in 3.0

 
HDLCompanion BrochureHDL Companion brochure
 
7 Minute overview of HDL Companion
 
Free 14 day trialDownload page
 
HDLCompanion pricingHDLCompanion pricing

HDL Companion White Papers

HDL level integration of IP blocks
Importing VHDL with references to the Xilinx Unisim package

 

 

 

 

 

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EASE – Graphical HDL Entry

EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you’re creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language – VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project.

Features & Benefits

  • Graphical design environment with automated generation of hierarchical VHDL or Verilog code
  • Standards compliant:
    – VHDL: IEEE-1076 87, 93 & 2008
    – Verilog: IEEE-1364 95, 2001
    – SystemVerilog IEEE-2005 / 2009
  • Virtual records to decrease diagram complexity and increase flexibility
  • True multi-user design environment and associated version control, managed by a sophisticated design environment browser
  • Push-button import of legacy Verilog or VHDL designs and extraction of graphical hierarchy
  • Integrates smoothly with the industry’s most popular simulators and synthesis tools
  • Platform independent database
  • Integrated HDL language editor
  • Hot error reporting
EASE Graphical HDL Entry

Explore EASE

 
EASE BrochureEASE Brochure
 
7 Minute overview of EASE
 
Free 14 day trialFree 14 day trial
 
EASE PricingEASE Pricing
toolsSupport page

White Papers and other documentation

Compilers for C/C++Real Time Operating SystemsDebuggers & JTAG EmulatorsEmbedded Software Testing solutionsMiddleware & SW componentsHW Testing solutions – Boundary-Scan (JTAG) & FunctionalOrganizing, Analyzing & Verification tools for HDL designs, FPGAs, Board schematic, PCB layout and Systems designersProtocol and Bus Analyzers & StimulatorsHome of CANopen, EtherCAT, PowerLink, ProfiNet– SW Protocols, Data loggers, Interfaces, devices & SolutionsIn-Circuit/Parallel Engineering & Production Device Programmers (Flash/EPROMs/CPLDs…)Video & Audio SW CODECs components

For more information: Ohad Beit-On ohad@sightsys.co.il 054-2584032